The present invention relates to a read-out control system for a control storage device in a data processing unit of a microprogram controlled type.
In general, the microprogram controlled type data processor is provided with a control storage device storing a microprogram having a number of microinstructions within a microprogram control device of a central processing unit. In this type data processor, a microinstruction read out from the control storage device is transferred through a microinstruction register to a decoder where the microinstruction is decoded to produce signals for controlling an arithmetic logic portion, as disclosed in U.S. Pat. No. 3,391,394.
The construction of this type data processor is as shown in FIG. 1 and operates as diagramatically illustrated in FIG. 2. When the CPU (central processing unit) executes a user instruction, a start address information A of a microprogram to control the execution of the user instruction is transferred through a signal line 11 to a selector switch 12. Upon receipt of the information A, the selector switch 12 selects the information A to send it onto an address line 13 at the leading edge of a machine clock signal as shown in FIG. 2A. The start address information A selected then is applied through a driver 14 to a control storage device 15. Upon application of the address information A, a microinstruction is read out from an address of the control storage device 15 specified by the start address information A.
The address information A is applied to one of the input terminals of an adder 16 where it is incremented by the value `1` inputted through a signal line 17 to produce address information A+1. Then, at the leading edge of the machine clock signal T1 shown in FIG. 2A, the microinstruction read out from the control storage device 15 (referred to as a microinstruction A in this case) is stored in a microinstruction register 18. See FIG. 2B.
The address information A+1 which is an output signal from the adder 16 is stored in the address register 19. At this time, when the microinstruction A designates a sequential read out of microinstructions from the control storage device 15, the selector switch 12 selects the address A+1 stored in the address register 19, as shown in FIG. 2D, and sends it onto the address line 13, as shown in FIG. 2C. Succeedingly, the next microinstruction A+1 is read out from the control storage device 15 in synchronism with the machine clock signal T2 shown in FIG. 2A.
If, for example, when the microinstruction A+2 read out from the control storage device into the microinstruction register 18, is a branch instruction, address information B set in an address field to which the program microinstruction A+2 is to be branched is sent out onto a signal line 20 to the selector switch 12. On the basis of the address information B, the selector switch 12 selects the address information B to send it onto the address line 13. The address information B then reads out a microinstruction B of the control storage device 15 specified by the information B. When an interrupt takes place in the CPU, the selector switch 12 selects a specified interrupt address and transfers it to the control storage device 15. As described above, the address circuit for the conventional control storage device 15 employs a logic circuit arrangement to prepare the address information of the next microinstruction by using the adder 16. Accordingly, when the number of bits of the address information increases, the circuit construction of the adder 16 is complicated in a like degree.
An example of this type address circuit is marketed with trade names "microprogram sequencers Am 2909 and Am 2911" by Advanced Micro Devices Inc. The detail of the microprogram sequencers is discussed in "The Am 2900 Family Data Book with Related Support Circuits" Copyright.COPYRGT.1978.